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cyrs1049dv33 4-mbit (512 k 8) static ram with radstop? technology cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-64292 rev. *e revised december 3, 2013 4-mbit (512 k 8) static ram with radstop? technology radiation performance radiation data total dose = ? 300 krad soft error rate (both heavy ion and proton) heavy ions ? 110 -10 upsets/bit-day with single-error correction, double error detection error detection and correction (sec-ded edac) neutron = 2.0 10 14 n/cm 2 dose rate > 2.0 10 9 (rad(si)/s) latch up immunity let = 120 mev.cm 2 /mg (125 ? c) processing flows q grade - class q flow in compliance with mil-prf 38535 v grade - class v flow in compliance with mil-prf 38535 prototyping options cypt1049dv33 protos with same functional and timing as flight units using non-radiation hardened die characteristics in a 36-pin ceramic flat package features temperature ranges ? military/space: ?55 c to 125 c high speed ? t aa = 12 ns low active power ? i cc = 95 ma at 12 ns (p max = 315 mw) low cmos standby power ? i sb2 = 15 ma 2.0 v data retention automatic power-down when deselected transistor-transistor logic (ttl) compatible inputs and outputs easy memory expansion with ce and oe features available in pb-free 36-pin ceramic flat package a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down ce we oe row decoder column decoder 512k x 8 array input buffer a 10 a 13 a 14 a 15 a 16 a 17 a 11 a 12 a 18 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 logic block diagram
cyrs1049dv33 document number: 001-64292 rev. *e page 2 of 16 contents functional description ..................................................... 3 selection guide ................................................................ 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 ac switching characteristics ......................................... 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagram ............................................................ 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 glossary .......................................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc? solutions ...................................................... 16 cypress developer community ................................. 16 technical support ................. .................................... 16
cyrs1049dv33 document number: 001-64292 rev. *e page 3 of 16 functional description the cyrs1049dv33 is a high-performance complementary metal oxide semiconductor (cmos) static ram organized as 512 k words by 8 bits with radstop? technology. cypress?s state-of-the-art radstop tec hnology is radiation hardened through proprietary design and process hardening techniques. the 4-mbit fast asynchronous sram with radstop technology is also qml v certified with defense logistics agency land and maritime (dlam). to write to the device, take chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the locati on specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. under these conditions, the c ontents of the memory location specified by the address pins appear on the i/o pins. see the truth table on page 11 for a complete description of read and write modes. the eight input or output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low) the cyrs1049dv33 is available in a ceramic 36-pin flat package with center power and ground (revolutionary) pinout. easy memory expansion is provided by utilizing oe , ce , and tri-state drivers. for best practice recommendations, refer to the cypress application note an1064, sram system guidelines . selection guide description military/space unit maximum access time 12 ns maximum operating current 95 ma maximum cmos standby current 15 ma pin configuration figure 1. 36-pin ceramic fl at package pinout (top view) [1] 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 12 13 16 15 29 30 18 17 20 19 27 28 25 26 22 21 23 24 nc a 0 a 1 a 2 a 8 a 7 a 11 a 10 dnu a 9 a 18 a 17 a 16 a 3 a 6 a 4 ce io 0 io 1 io 2 io 3 we a 5 a 13 a 14 io 4 io 5 io 6 io 7 oe a 15 v cc v cc gnd gnd a 12 10 note 1. nc pins are not connected on the die.
cyrs1049dv33 document number: 001-64292 rev. *e page 4 of 16 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................ ?65 ? c to +150 ? c ambient temperature with power applied .......................................... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [2] ................................?0.3 v to +4.6 v dc voltage applied to outputs in high z state [2] ................................ ?0.5 v to v cc + 0.5 v dc input voltage [2] ............................. ?0.5 v to v cc + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, method 3015) ................................. > 2001 v latch up current ..................................................... > 140 ma operating range range ambient temperature v cc speed military/space ?55 ? c to +125 ? c3.3 v ? 0.3 v 12 ns dc electrical characteristics over the operating range parameter description test conditions military/space unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ?v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih [2] input high voltage 2.0 v cc + 0.3 v v il [2] input low voltage ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc 83 mhz ? 95 ma 66 mhz ? 85 ma 40 mhz ? 75 ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce > v ih v in > v ih or v in < v il , f = f max ? 15 ma i sb2 automatic ce power-down current ? cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ? 15 ma note 2. v il(min) = ?2.0 v and v ih(max) = v cc + 2 v for pulse durations of less than 20 ns.
cyrs1049dv33 document number: 001-64292 rev. *e page 5 of 16 capacitance parameter [3] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 8 pf c out i/o capacitance 8pf thermal resistance parameter [3] description test conditions ceramic flat package unit ? jc thermal resistance (junction to case) test according to mil-prf 38538 3.6 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms [4] 90% 10% 3.0 v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5 v (a) 3.3 v output 5pf (c) r 317 ? r2 351 ? high-z characteristics (b) notes 3. tested initially and after any design or process changes that may affect these parameters. 4. ac characteristics (except high z) are tested using the load conditions shown in figure 2 (a). high z characteristics are tested fo r all speeds using the test load shown in figure 2 (c).
cyrs1049dv33 document number: 001-64292 rev. *e page 6 of 16 data retention characteristics over the operating range parameter description conditions [5] min max unit v dr v cc for data retention ? 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ?15 ma t cdr [6] chip deselect to data retention time ?0?ns t r [7] operation recovery time ? 12 ? ns data retention waveform figure 3. data retention waveform 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc notes 5. no input may exceed v cc + 0.3 v. 6. tested initially and after any design or process changes that may affect these parameters. 7. full device operation requires linear v cc ramp from v dr to v cc(min) > 50 ? s or stable at v cc(min) > 50 ? s.
cyrs1049dv33 document number: 001-64292 rev. *e page 7 of 16 ac switching characteristics over the operating range parameter [8] description military/space unit min max read cycle t power [9] v cc (typical) to the first access 100 ? ? s t rc read cycle time 12 ? ns t aa address to data valid ? 12 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 12 ns t doe oe low to data valid ? 6 ns t lzoe oe low to low z [10] 0 ? ns t hzoe oe high to high z [10, 11] ? 6 ns t lzce ce low to low z [10] 3 ? ns t hzce ce high to high z [10, 11] ? 6 ns t pu ce low to power-up 0 ? ns t pd ce high to power-down ? 12 ns write cycle [12, 13] t wc write cycle time 12 ? ns t sce ce low to write end 8 ? ns t aw address setup to write end 8 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 8 ? ns t sd data setup to write end 6 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [10] 3 ? ns t hzwe we low to high z [10, 11] ? 6 ns notes 8. test conditions assume signal transition time of 3 ns or less , timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 9. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access is performed. 10. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , t hzbe is less than t lzbe , and t hzwe is less than t lzwe for any given device. 11. t hzoe , t hzce , t hzbe, and t hzwe are specified with a load capacitance of 5 pf as in part (c) of figure 2 on page 5 . transition is measured when the outputs enter a high impedance state. 12. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write and the transition of either of these signals can terminate the write. the input data setup and hold timing should be referenced to the leading edge of the sig nal that terminates the write. 13. the minimum write cycle time for write cycle no. 4 (we controlled, oe low) is the sum of t hzwe and t sd .
cyrs1049dv33 document number: 001-64292 rev. *e page 8 of 16 switching waveforms figure 4. read cycle no. 1 [14, 15] figure 5. read cycle no. 2 (oe controlled) [15, 16] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current notes 14. device is continuously selected. oe , ce = v il . 15. we is high for read cycle. 16. address valid prior to or coincident with ce transition low.
cyrs1049dv33 document number: 001-64292 rev. *e page 9 of 16 figure 6. write cycle no. 1 (ce controlled) [17, 18] figure 7. write cycle no. 2 (we controlled, oe high during write) [17, 18] switching waveforms (continued) t wc data in valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 19 notes 17. data i/o is high impedance if oe = v ih. 18. if ce goes high simultaneously with we going high, the output remains in a high impedance state. 19. during this period the i/os are in the output state and input signals should not be applied.
cyrs1049dv33 document number: 001-64292 rev. *e page 10 of 16 figure 8. write cycle no. 3 (we controlled, oe low) switching waveforms (continued) data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 20 note 20. during this period the i/os are in the output state and input signals should not be applied.
cyrs1049dv33 document number: 001-64292 rev. *e page 11 of 16 truth table ce oe we i/o 0 ?i/o 7 mode power h x x high z power-down standby (i sb1 or i sb2 ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc )
cyrs1049dv33 document number: 001-64292 rev. *e page 12 of 16 ordering information the following table contains only the parts that are currently av ailable. if you do not see what you are looking for, contact y our local sales representative. for more informa tion, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices. ordering code definitions speed (ns) ordering code package diagram package type operating range 12 cyrs1049dv33-12fzmb 001-67583 36-pin ceramic flat package burn-in 12 cypt1049dv33-12fzmb 001-67583 36-pin ceramic flat package, prototype part burn-in 12 5962F1123501QXA 001-67583 36-pin ceramic flat package, dlam part burn-in 12 5962f1123501vxa 001-67583 36-pin ceramic flat package, dlam part burn-in contact your local cypress sales repres entative for availability of these parts temperature range: b = burn-in temperature grade thermal rating: x = blank or m blank = non-military; m = military package type: fz = 36-pin ceramic fp speed: 12 = 12 ns v33 = voltage range (3 v to 3.6 v) d= 90 nm technology data width: 9 = 8 bits density: 04 = 4-mbit 1 = fast asynchronous sram family xx = rs or pt rs = radstop; pt = prototype company id: cy = cypress 1 cy 04 12 fz b xx 9 d v33 x -
cyrs1049dv33 document number: 001-64292 rev. *e page 13 of 16 package diagram figure 9. 36-pin ceramic flat pack (s older seal lid) packa ge outline, 001-67583 001-67583 *b
cyrs1049dv33 document number: 001-64292 rev. *e page 14 of 16 acronyms document conventions units of measure glossary acronym description ce chip enable cmos complementary metal oxide semiconductor dlam defense logistics agency land and maritime dnu do not use edac error detecti on and correction i/o input/output let linear energy transfer oe output enable qml qualified manufacturers list sec-ded single error correcti on ? double error detection sel single-event latch-up sram static random access memory tsop thin small outline package ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz a microampere s microsecond ma milliampere ns nanosecond % percent pf picofarad vvolt wwatt total dose permanent device damage due to ions over device life heavy ion instantaneous device latch up due to single ion let linear energy transfer (measured in mevcm 2 ) krad unit of measurement to determine device life in radiation environments. neutron permanent device damage due to energetic neutrons or protons prompt dose data loss of permanent device damage due to x-rays and gamma rays <20 ns radstop technology cypress's patented rad hard design methodology qml v space level certification from dscc. dlam defense logistics agency land and maritime lsbu logical single bit upset. single bits in a single correction word are in error. lmbu logical multi bit upset. multiple bits in a single correction word are in error
cyrs1049dv33 document number: 001-64292 rev. *e page 15 of 16 document history page document title: cyrs1049dv33, 4-mbit (512 k 8) static ram with radstop? technology document number: 001-64292 rev. ecn no. origin of change submission date description of change ** 3098986 hrp 12/01/2010 new data sheet. *a 3181475 pras 02/24/2011 updated package diagram (replaced 44-pin tsop ii package with 36-pin flat package). *b 3438781 hrp 11/14/2011 updated package diagram (to current revision). *c 3554946 hrp 03/19/2012 changed status from preliminary to final. updated radiation performance (updated radiation data , prototyping options ). updated features (added (p max = 315 mw)). updated functional description (added the paragraph ?easy memory expansion is provided by utilizing oe , ce , and tri-state drivers.?). updated maximum ratings (dc voltage applied to outputs in high z state, dc input voltage). updated ac switching characteristics (changed the maximum value of t doe parameter from 7 ns to 6 ns). updated ordering information (additional part numbers added). *d 3887928 hrp 02/07/2013 updated radiation performance (updated processing flows (replaced v grade with q grade), prototyping options (added non-radiation hard, replaced v grade with q grade)). updated ordering information (updated part numbers). *e 4208547 vini 12/03/2013 updated radiation performance : updated processing flows : added ?v grade - class v flow in compliance with mil-prf 38535?. updated prototyping options : updated the first bullet as ?cypt1049dv33 protos with same functional and timing as flight units using non-radiation hardened die?. updated ordering information (updated part numbers). updated package diagram : spec 001-67583 ? changed revision from *a to *b. updated in new template. completing sunset review.
document number: 001-64292 rev. *e revised december 3, 2013 page 16 of 16 radstop? is a trademark of cypress semiconductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. cyrs1049dv33 ? cypress semiconductor corporation, 2010-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive aerospace & defens e cypress.com/aero clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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